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CoreU1LL UTOPIA Level 1 Link-Layer Interface
Device Requirements
CoreU1LL can be implemented in either ProASIC PLUS or Axcelerator device families. Table 1 indicates the number of
core logic cells required in each technology.
Table 1 ? Device Utilization and Performance
Cells or Tiles
Total Utilization
ProASIC
Family
Fusion
ProASIC3/E
PLUS
Axcelerator
Sequential
51
51
51
53
Combinatorial
66
66
79
64
Device
AFS060
A3P060
APA075
AX125
Percentage
7.8%
7.8%
4.2%
6.0%
Performance
>25 MHz
>25 MHz
>25 MHz
>25 MHz
UTOPIA Interface
CoreU1LL implements a standard 8-bit point-to-point
PHY-Layer interface that supports cell lengths of either
53 or 54 bytes. If the cell_size bit is low, a 53-byte cell is
transferred and the UDF2 byte is inserted on ingress to,
and dropped on egress from, the user interface;
otherwise, 54 bytes are transferred. The UTOPIA
interface signals are summarized in Table 2 .
sends 53 bytes (or 54 bytes) and does not monitor
u1_tx_clav during cell transfers.
u1_tx_clk
u1_tx_clav
u1_tx_en
u1_tx_soc
Table 2 ? UTOPIA Interface Signals
Signal
Type Description
u1_tx_data
H1 H2
u1_tx_clk
u1_tx_clav
u1_tx_en
u1_tx_soc
u1_tx_data
u1_rx_clk
u1_rx_clav
u1_rx_en
u1_rx_soc
u1_rx_data
In
In
Out
Out
Out
In
In
Out
In
In
Tx interface clock
Active high cell buffer space available
Active low data transfer enable
Active high start-of-cell indication
8-bit egress data
Rx interface clock
Active high cell buffer space available
Active low data transfer enable
Active high start-of-cell indication
8-bit ingress data
Figure 2 ? Tx Start of Cell
If the user interface indicates that there are no more cells
to send, or if polling during the current cell transfer
indicates that the PHY-Layer device is not ready to accept
another cell, the CoreU1LL deselects the physical
interface by deasserting u1_tx_en after the last word of
the transfer ( Figure 3 ).
u1_tx_clk
u1_tx_clav
u1_tx_en
u1_tx_soc
Tx Interface (Egress)
u1_tx_data
P51 P52 P53 P54
XX
The process of transferring a cell on the UTOPIA level 1
Tx interface begins with r_avail. User logic asserts r_avail
high whenever it has a cell available to send. The
CoreU1LL waits until the PHY-Layer device indicates that
it is ready to receive a cell by asserting u1-tx_clav high.
To begin sending cells on the Tx interface, the CoreU1LL
asserts u1_tx_en low ( Figure 2 ). CoreU1LL simultaneously
asserts u1_tx_soc and u1_tx_data ( Figure 2 ). The core
Figure 3 ? Tx Transfer Complete
If the user interface has another cell to send to the PHY-
Layer device, and if polling during the current cell
indicates that the PHY-Layer device can accept another
2
v4.0
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相关代理商/技术参数
COREU1LL-EV 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1LL UTOPIA Level 1 Link-Layer Interface
COREU1LL-SN 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1LL UTOPIA Level 1 Link-Layer Interface
COREU1LL-SR 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1LL UTOPIA Level 1 Link-Layer Interface
COREU1LL-UR 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1LL UTOPIA Level 1 Link-Layer Interface
COREU1LL-XX 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1LL UTOPIA Level 1 Link-Layer Interface
COREU1PHY-AN 制造商:Microsemi Corporation 功能描述:COREU1PHY-UTOPIA LEVEL 1 PHY INTERFACE - Virtual or Non-Physical Inventory (Software & Literature)
COREU1PHY-AR 功能描述:IP MODULE COREU1PHY RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384
COREU1PHY-EV 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1PHY - UTOPIA Level 1 PHY Interface